1. Field of the Invention
The present invention relates to a stacked type chip package structure and a method of fabricating the same. More particularly, the present invention relates to a stacked type chip package structure on which a thinning process is performed and a method of fabricating the stacked type chip package structure.
2. Description of Related Art
Currently, electronic devices commensurate with market demands and advancement of manufacturing technologies are progressing. In consideration of the portability of and growing demands for computer, communication and consumer (3C) electronic products, a conventional single chip package structure gradually fails to comply with the requirements in the market. Namely, trends of lightness, thinness, shortness, smallness, compactness, high density, and low costs must be taken into account in designing the products. As such, in view of the requirements for lightness, thinness, shortness, smallness, and compactness, integrated circuits (IC) with various functions are stacked in different manners for reducing dimensions and thickness of package products, which has become a mainstream strategy in the package market. At present, the package products having a package on package (POP) structure or a package in package (PIP) structure are researched and developed in response to such trend.
FIG. 1 is a schematic cross-sectional view of a conventional PIP structure. As indicated in FIG. 1, an individual package 120 in which no solder balls are installed is stacked on a chip 114 of another package 110 in the PIP structure, and a spacer 130 is disposed between the package 120 and the chip 114. After that, a molding process is performed on both the packages 120 and 110. The package 110 has a substrate 112, the chip 114, and a chip 116. The chips 114 and 116 are stacked on the substrate 112 in sequence. By contrast, the package 120 has a substrate 122 and a chip 124 stacked on the substrate 122.
FIG. 2 is a schematic cross-sectional view of a conventional POP structure. As shown in FIG. 2, in the POP structure, two individual packages 210 and 220 are packaged and inspected first, and then the two packages 210 and 220 are adhered and electrically connected to each other through solder balls 230. Thereby, the POP structure is formed. The package 210 has a substrate 212 and chips 214 and 216 stacked on the substrate 212. By contrast, the package 220 has a substrate 222 and a chip 224 stacked on the substrate 222.
With the increasing complexity and the enhancement of the functions of the electronic devices, the required number of the chips that are stacked in the POP structure and the PIP structure is increased day by day. As such, it is imperative to control the thickness of the chips, so as to reduce space occupied by the stacked chips and further reduce the thickness of the chip package structure in a package process.